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UTS being ISO 9001:2008 certified company, follows standard procedures while executing the projects, to ensure  long term success to client, by delivering fully verified, reusable and well documented software and hardware modules.
Workshop on
Low power and mixed signal VLSI, 01 - 03 Jan 2008
Unifying Software & Hardware
UTS being an IP core developer in several disciplines, it has been involved in design and development of VLSI / FPGA / Embedded platform based applications in several state of the art technologies. This R&D experiance enables UTS to offer world class products & services to VLSI and Embedded industry  with less design turn around time.
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    Topic: Low power VLSI design issues
    Speaker: Vasu, Senior application engineer, VLSI&EH team.
    Event : Low power and mixed signal VLSI, 01 - 03 Jan 2008
    Organized by : Aurora's engineering college, Hyderabad, INDIA.
    Brief description: Low power VLSI design is the most challenging and demanding area in VLSI design. The talk covers the following aspects. fundamentals of energy, power calculations, Motivation for low power VLSI design static, dynamic, leakage power components Various leakage mechanism Low power design at system level Low power design at technology level, device level, circuit level, gate level, architecture level, system level Examples in all above categories Case study - Architecture level power reduction using distributed arithmetic principle. Xilinx Xpower tool and its usage in studying low power architectures.

Down load the slides

thanks to Shri Bharadwaj Amrutur for his course slides at http://ece.iisc.ernet.in/~amrutur/amrutur.html

Contact vasu@unistring.com for further information or technical material on this event.
Date 01 - 03 Jan 2008
Venue Seminar Hall, Aurora's Engineering College(AEC), Bohngir, Nalogonda Dist, Telangana.
Association with Aurora's Engineering College(AEC), Bohngir
Number of Participants 50+
Participants from M.Tech students of this college AEC, Hyderabad.

Contact UTS for more details