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UTS offers wide range of products in Wireless communications, RADAR, SONAR, EDA and Energy sectors. With the long standing IP core development experience, UTS offered products use latest algorithms and technological developments, to provide better features than existing products. UTS products take best out of the latest FPGA/GPU/CPU technologies to offer improved features compared to legacy processor based products.
UTS being ISO 9001:2008 certified company, follows standard procedures while executing the projects, to ensure  long term success to client, by delivering fully verified, reusable and well documented software and hardware modules.
COMINT Signal Detection and Classification - IP suite
Unifying Software & Hardware
COMINT Signal Detection and Classification is very crucial operation in Communication Electronic Warfare (EW) operations. The present day radios with time and frequency hopping techniques make the interception challenging with conventional search receivers. The Low Probable of Intercept (LPI) waveforms are popular today in Radios offered worldwide. The advancements in VLSI and RF technologies are resulting in Software Defined Radio (SDR) topology based radios, which are difficult to intercept.

The UTS’s Signal Detection and Classification (SDC) IP suite is ideal for realizing modern day search and direction finding (DF) solutions. The IP suite is bundled with several algorithms which provide options for automatic, semi-automatic and manual based signal detection & classification, enabling the product designer to meet different category of search applications.

The processing stages in the SDC IP are described in below figure. At each stage the signals are available for user access. This feature allows user to unplug one stage of algorithm module and replace with his own algorithm. Also when multi core processor implementation is desired, each module can be made to run on designated core.
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COMINT Signal Detection and Classification - IP suite

                        Contact us at ewip@unistring.com for more details
Figure 1. Algorithm modules in Signal Detection and Classification (SDC) IP suite
The first stage of SDC IP receives data from ADC and carries out Digital Down Conversion (DDC) as per the set bandwidth of the signal. This module can take real or complex data as input. Digital filtering at this stage allows user to remove non-ideal components (such as spurious) and improve dynamic range.
At STFT stage the signal's spectrum is computed for windowed input samples. Window overlapping is allowed to improve time resolution. Different FFT sizes can be selected based on the frequency resolution requirements.  Window function can be selected among multiple functions (Rectangular, Triangular, Hamming, Hanning, Blackman, Gaussian, Barlett-Hann, Kaiser and Blackman Harris) in spectrum estimator before FFT is provided. The Polyphase-FFT is available as optional feature.
Noise estimation algorithm provides different algorithms for estimation of noise. User can select required algorithm to configure threshold accordingly. Instead user also can provide fixed threshold value.
The Signal detection module applies the threshold on bin by bin basis and detects the presence of signal. This module generates the report with time and frequency information. The signal detected even in one FFT frame also leads to a report, which is desirable feature for LPI signals.
The signal classification and parameter estimation module reads the reports from signal detection stage. The signal classification module performs long term histogramming and time frequency analysis and finally declares the emitters in the present scenario. The band code (Actual RF value which is converted to IF and fed to ADC) along with detected FFT bin together is used to generate the true frequency value. Hence the algorithms in final stage provide the detected signals results with absolute frequency, BW and life time.
1.  Key features of SDC IP suite
The following are the key features offered by UTS’s Signal Detection and Classification IP suite.
1)     Internal clock management compatible to Xilinx 5,6, and 7 Family FPGAs.
2)     Can be easily integrated with UTS offered other IP cores and GUI applications.
3)      Most of the algorithms are available for both FPGA and processor architectures (to be     selected at the time of ordering). User can select the required configuration based on the target hardware.
4)      Run time selectable window function (Rectangular, Triangular, Hamming, Hanning, Blackman, Gaussian, Barlett-Hann, Kaiser and Blackman Harris). The Polyphase windowing is available as optional feature.
5)      Adjustable overlapping factor to achieve necessary time resolution  (Over lapping factor of 0%, 25% and 50%).
6)      Multiple FFT sizes (512/1K/2K/4K/8K/16K/32K) to achieve necessary frequency resolution.
7)     Spectrum averaging with run time adjustable average factor (1,2,4,8,16, 32,..... 1024)
8)     FPGA to external interface is available both on soft-processor core (Microblaze) and Hardprocessor core (ARM9 of Zynq).
9)     Automatic noise estimation and options for manual override for threshold setting
10)   Algorithms to detect Fixed frequency, Burst and Frequency hopper (FH) detection.
11)   Algorithms to de-interleave hops of different FH emitters.

2. Time frequency analysis - Options to optimize for Frequency and Time resolution
The time-frequency tradeoff is most crucial algorithmic limitation in detecting the LPI signals. The UTS IP cores offer run time configurable options to adjust the time resolution and frequency resolution based on requirements.
Ex1 :
When 20MHz input signal bandwidth is processed with 25MHz clock the following minimum time resolution can be achieved.
Minimum time resolution of  10.2 usec with 512 point FFT for 20MHz input bandwidth.
This configuration results in frequency resolution of 48.8 KHz
Ex 2:
When 20MHz input signal bandwidth is processed with 25MHz clock the following minimum frequency resolution can be achieved.
Minimum frequency resolution of 770 Hz with 32K point FFT.
This configuration results in time resolution of 1.3 msec.

3. Specifications
Category Specification Value
DDC stage  
  Maximum input sampling rate 250 MHz
  Decimation range 2 to 16
  Maximum output bandwidth 100 MHz
  Minimum output bandwidth 12.5 MHz
STFT stage  
  Maximum input clock/sampling rate 125 MHz
  FFT size 512/1K/2K/4K/8K/16K/32K
  Window function Rectangular, Triangular, Hamming, Hanning, Blackman, Gaussian, Barlett-Hann, Kaiser and Blackman Harris
  Averaging factor 1,2,4,8,16, 32,..... 1024
  Overlapping factor 0%, 25% and 50%
Noise estimation & Threshold    
  Algorithm selection Mean, Rank order Filtering (ROF)
Image processing algorithm based
  Threshold type Automatic / manual.
Event Detection and report generation 
  Report parameters RF band code (PLL set value)Time of Intercept (TOI)Centre Frequency Max power frequencyBandwidth bins
  Bin merging Adjustable thresholds
Signal classification  
  Signal Detection category Fixed FrequencyBurst
Frequency hopping
  Parameters Frequency
Burst/Hop duration
Time of interception
Life time
  Other Reports and database with signal history.