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The Coherent FSK modulator and demodulator cores, provided by UTS are FPGA proven variable data rate IP cores, which can meet large class of wired and wireless communication needs. This IP core provides several run time controls, to make it suitable for software defined radio and cognitive radio applications. Please refer to Non-Coherent FSK page if carrier synchronization is not desired for your application.. The UTS IP core with Gaussian pulse shaping option can be used for Minimum shift keying (MSK), which is a spectrally efficient form of Coherent FSK.
UTS offers IPs under flexible licensing models, to meet requirements of different category of users. The low cost reference designs are distinguished from IPs with less (or no) document (end user/project) execution for licensing.  Read more from IP main page.

UTS offers transparent and pre-committed pricing model for a minimum period of five years from the date of order  to migrate from per product based licensing to unlimited licensing or source code licensing models. With this the system developers have clear estimate of the cost in the volume production, right at the time of prototype development.

IP based on user specification

UTS also takes up development of complex algorithms based on the end performance specifications as per user requirements. In certain fields UTS also takes up this development on No cost - No commitment (NCNC) model. Based on the project category the UTS share on IP rights can be worked out for mutual benefit.

Refer to the links given for obtaining information of different IPs. Request for more information or demo  by emailing to ewip[at the rate]unistring.com
Unifying Software & Hardware
Coherent FSK Modulator and Demodulator - IP core

UTS-CFSK-MOD-V3.3 (only modulator)
UTS-CFSK-DEMOD-V3-V3.5 (only demodulator)

Contact us with your specifications for obtaining quote specific to your requirements.
High data rate FPGA proven Coherent FSK IP core
Telemetry links
High band width point to point wireless links
Software Defined Radios
Cognitive Radios
UAV to Ground Communication
Satellite communication
Test equipment
Military & Home land security
Latest mobile communication applications
Key features
Architecture & Core description
Ordering information (P/N)
Area, Speed and Through put bench marks for Xilinix FPGAs
Tested on all Xilinx 5,6,7 device FPGAs
High frequency of operation - 250 MHz
Run time configurable symbol rates - 8 ksps to 12 Msps
     -- Date rate with FSK-2 :  8 Kbps to 12 Mbps
     -- Date rate with FSK-4 :  16 Kbps to 24 Mbps
Area Optimized design( resource utilization benchmarks are given below)
Selectable pulse shaping filter (SRRC, RRC, Gaussian) and rolloff  factors
Runtime User loadable filter coefficients for pulse shaping
Run time controllable thresholds to work under different signal conditions (symbol lock etc)
Automatic constellation rotation detection and symbol to bit decoding
FIFO interface to Soft processor (Microblaze) or Hard processor (ARM9 of Zynq)
Ethernet software driver to interface to PC or Embedded unit over LAN
Licensing terms
Other Required / Related IPs


Wide band DDC When the input is from ADC (real signal), then DDC will be required to down convert to complex base band signal.
Time division mux and demux When multiple channel data need to be transmitted/received these multiplexers and demultiplexers are suitable to be used along with modulators and demodulators.
Channel encoders and decoders .In wireless communication at low SNRs, the channel encoders and decoders are appropriate to be used along with modulators and demodulators.
The Coherent Frequency shift Keying (C-FSK) modulator and demodulator cores, provided by UTS are designed with speed and resource wise optimized techniques for FPGAs. The designs are tested for several corner cases, including tight placement constraints in small FPGAs and working at maximum clock rates. The block diagram of C-FSK modulator is given in below figure. The default configuration of core can work for FSK-2 and FSK-4 schemes. However based on requirements the core can be modified for any number of tones.
Fig. High level block diagram C-FSK modulator
The data rate controller block accepts the symbol rate word and generates "ready for bit" enable signal. The data sourcing FIFO can output one bit with this enable become '1'. The date rate controller block also generates enables for other modulator blocks based on symbol rate value. The bit to symbol mapping block generates frequency deviation based on the input bit(s). The pulse shaping block can perform optionally SRRC (square root raised cosine) or RRC (root raised cosine) or Gaussian with different roll off factors. Dynamically required filter coefficients can also be loaded.

The frequency deviations with/without pulse shaping are used to alter the instantaneous frequency. The instantaneous frequency set to digital Numerically Controlled Oscillator (NCO) generates the FSK modulated signals. The digital up converter (DUC) with fractional interpolator can produce output signal with required sampling rate. This feature enables driving any external Digital to Analog Converter (DAC) with required sampling rate.
Fig. High level block diagram C-FSK demodulator
The block diagram of Coherent FSK demodulator is shown in above figure. The tones are approximate frequencies used for each symbol. The DPLL block locks the local carrier phase with the input signal. The error for DPLL signal is derived from the low pass filters corresponding to each tone. The symbol timing recovery block computes one sample per symbol, by using timing error detector (TED) loop. Optionally the pulse shaping can be done for matched filtering. The detected amplitudes for each tone can be used for plotting constellation. The symbol to bit mapping block can assign bits for each symbol based on the selected scheme. User can allocate any bit pattern for symbol, through run time configurable port.

This feature enables to use UTS - C-FSK demodulator with any frame synchronization modules such as E1/T1/E2/E3/T2/T3.  The demodulated symbol and bit are the final outputs of FSK demodulator.

The run time configurability of M-ary scheme (FSK-2,4), frequency values for each symbol and symbol rate makes the UTS FSK demodulator suitable for software defined radio and cognitive radio applications.
Verification of FSK on Xilinix FPGAs
FSK-2 Modulator
IP and configuration Resource utiilztion Maximum clock Speed
(max possible symbol rate)
FSK-2 Modulator
Xilinx Virtex-6 FPGA
Slices -  14520
DSP48 - 38
BRAM - 21
  210 MHz
(15 Msps)
FSK-2 Demodulator
IP and configuration Resource utiilztion Maximum clock Speed
(max possible symbol rate)
FSK-2 DeModulator
Xilinx Virtex-6 FPGA
  Slices - 22450
DSP48 - 52
BRAM - 54
  240 MHz
  (15 Msps)
FSK-4 Modulator
FSK-4 Demodulator
IP and configuration Resource utiilztion Maximum clock Speed
(max possible symbol rate)
FSK-4 Modulator
Xilinx Virtex-6 FPGA
Slices -  18920
DSP48 - 48
BRAM - 32
    210 MHz
(15 Msps)
IP and configuration Resource utiilztion Maximum clock Speed
(max possible symbol rate)
FSK-4 DeModulator
Xilinx Virtex-6 FPGA
Slices - 42376
DSP48 - 64
BRAM - 76
    240 MHz
  (15 Msps)
Contact UTS for obtaining these details.
Note that these results are only indicative of approximate area utilization and speed. Depending on the required features, it is possible to further optimize to improve speed and reduce resouce utilization. Contact UTS for obtaining details specific to your target FPGA family and device.

Also note that major BRAM resources are used by Chipscope memory (for in chip debugging), which can be removed in the production version. At least 50% of BRAM resources will get reduced.