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IP and configuration Resource utiilztion Maximum clock Speed
(max possible symbol rate)
CMA / MMA Blind Adaptive Equalizer
Xilinx Virtex-6 FPGA
Slices -  8230
DSP48 - 146
BRAM - 4
  200 MHz
(40 Msps)
The Constant Modulus Algorithm (CMA) and Multi-Modulus Algorithm (MMA) based Adaptive blind equalizer is useful realizing wireless radio in highly fading conditions. This IP core provides several run time controls, to make it suitable for software defined radio and cognitive radio applications.
UTS offers IPs under flexible licensing models, to meet requirements of different category of users. The low cost reference designs are distinguished from IPs with less (or no) document (end user/project) execution for licensing.  Read more from IP main page.

UTS offers transparent and pre-committed pricing model for a minimum period of five years from the date of order  to migrate from per product based licensing to unlimited licensing or source code licensing models. With this the system developers have clear estimate of the cost in the volume production, right at the time of prototype development.

IP based on user specification

UTS also takes up development of complex algorithms based on the end performance specifications as per user requirements. In certain fields UTS also takes up this development on No cost - No commitment (NCNC) model. Based on the project category the UTS share on IP rights can be worked out for mutual benefit.

Refer to the links given for obtaining information of different IPs. Request for more information or demo  by emailing to ewip[at the rate]unistring.com
Unifying Software & Hardware
CMA / MMA Fractional Blind Equalizer - IP core

UTS-CMMA-R4

Contact us with your specifications for obtaining quote specific to your requirements.
Applications
High data rate equalizer IP core for wireless communications
High band width point to point wireless links
Software Defined Radios
Telemetry links
UAV to Ground Communication
Test equpiment
Military & Home land security
Key features
Architecture & Core description
Ordering information (P/N)
Area, Speed and Through put bench marks for Xilinix FPGAs
Tested on all Xilinx 5,6,7 device FPGAs
Equalization length can be configured (factory configuration) from 1 symbol period to 10 symbol periods.
Number of samples in symbol can be configured(factory configuration)
Area Optimized design( resource utilization benchmarks are given below)
Can be Interfaced to UTS demodulators
Run time configurable CMA / MMA option
Run time loadable magnitude levels
Can be used along with PSK-2/4/8, QAM-4/8/16/32/64 and FSK-2/4 demodulator IP cores
Licensing terms
Other Required / Related IPs

   IP

    Purpose
Wide band DDC When the input is from ADC (real signal), then DDC will be required to down convert to complex base band signal.
Modulators and Demodulators Wide band wireless communication links can be realized with UTS modem IP cores and equalizer cores.
Channel encoders and decoders .In wireless communication at low SNRs, the channel encoders and decoders are appropriate to be used along with modulators and demodulators.
The Constant Modulus Algorithm (CMA) is stochastic gradient-descent type, which adjusts the equalizer filter coefficients in the direction of the negative gradient. The basic algorithm can be described as given in below equation. The filter coefficients w are updated after every cycle based on error.



The is the step size, which can be configured to adjust the convergence rate of adaptive algorithm. The e(n) is the error signal of the algorithm, while (.)* denotes complex conjugation. The iterative computations of filter coefficients w(n+1) from previous cycle coefficient values w(n). The CMA/MMA blind adaptive equalizers cores, provided by UTS are designed with speed and resource wise optimized techniques for FPGAs. The designs are tested for several corner cases, including tight placement constraints in small FPGAs and working at maximum clock rates. The high level block diagram of blind equalizer is given in below figure.
Fig. High level CMA / MMA blind equalizer
Verification on Xilinix FPGAs
Contact us for more details
w(n + 1)  = w(n) + e(n)x*(n)
Note that these results are only indicative of approximate area utilization and speed. Depending on the required features, it is possible to further optimize to improve speed and reduce resouce utilization. Contact UTS for obtaining details specific to your target FPGA family and device.

Also note that major BRAM resources are used by Chipscope memory (for in chip debugging), which can be removed in the production version. At least 50% of BRAM resources will get reduced.