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   IP and configuration     Resource utiilztion     Speed Suitable end usage
 
Slices(reg)
available-%

DSP48 Used/availab le-%

Block
RAM’S
   
Goertzel -Device- Spartan3E

1660/4656 - 35%
   
25 MHz(33.099 MHz)


DTMF applications

Goertzel -Device:Sparta n605

910  /18224 -   4%

24  / 32    75%

2  / 32  -

6%


25 MHz(75 MHz)



DTMF applications

Goertzel Device:Vertex-6
.
910  / 18224   - 4%

24  / 32 -   75%

2  /32-

6%


75 MHz




DTMF applications
The goertzel algorithm is area efficient approach for computing spectral energy on a single frequency for a digital input signal. The UTS provided goertzel IP core is useful for area optimized applications where energy on single frequency computation is required on a given FFT specification.




UTS offers IPs under flexible licensing models, to meet requirements of different category of users. The low cost reference designs are distinguished from IPs with less (or no) document (end user/project) execution for licensing.  Read more from IP main page.

UTS offers transparent and pre-committed pricing model for a minimum period of five years from the date of order  to migrate from per product based licensing to unlimited licensing or source code licensing models. With this the system developers have clear estimate of the cost in the volume production, right at the time of prototype development.


IP based on user specification

UTS also takes up development of complex algorithms based on the end performance specifications as per user requirements. In certain fields UTS also takes up this development on No cost - No commitment (NCNC) model. Based on the project category the UTS share on IP rights can be worked out for mutual benefit.

Refer to the links given for obtaining information of different IPs. Request for more information or demo  by emailing to ewip[at the rate]unistring.com
Unifying Software & Hardware
GOERTZEL ALGORITHM - IP core
UTS-GZL--BASIC-V1


Contact us with your specifications for obtaining quote specific to your requirements.
Applications
Area optimized spectrum estimation for a single bin (FFT) category - IP core
Used in DTMF applications
Embedded long distance control signal transmission
New telephone and voice chipsets
Medicine, Wildlife study and management
Miiltary & Home land security
Enemy intelligence
Software Defined Radio, Cognitive Radio
Key features
Architecture & Core description
Ordering information (P/N)
Area, Speed and Through put bench marks for Xilinix FPGAs
Accepts streaming input signal
Dynamic start/reset signal
Tested on all Xilinx Spartan series 3, 3E, 601,605 devices and vertex device FPGAs
High frequency of operation - 50 MHz
Run time bin number selection
Area Optimized design( resource utilization benchmarks are given below)
Runtime User loadable filter coefficients based upon bin number
Licensing terms
Block diagram:
Other Required / Related IPs
   IP     Resource utiilztion
Wide band DDC  
Time division mux and demux  
Channel encoders and decoders .
Results