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High data rate FPGA proven Image Processing IP core

The Morphological Image processing IP core provided by UTS are FPGA proven high data rate Image processing IP solution. Mathematical morphology (MM) is a theory and technique for the analysis and processing of geometrical structures. These IP cores can meet high speed image processing and satellite applications on FPGA’s.
UTS offers IPs under flexible licensing models, to meet requirements of different category of users. The low cost reference designs are distinguished from IPs with less (or no) document (end user/project) execution for licensing.  Read more from IP main page.

UTS offers transparent and pre-committed pricing model for a minimum period of five years from the date of order  to migrate from per product based licensing to unlimited licensing or source code licensing models. With this the system developers have clear estimate of the cost in the volume production, right at the time of prototype development.


IP based on user specification

UTS also takes up development of complex algorithms based on the end performance specifications as per user requirements. In certain fields UTS also takes up this development on No cost - No commitment (NCNC) model. Based on the project category the UTS share on IP rights can be worked out for mutual benefit.

Refer to the links given for obtaining information of different IPs. Request for more information or demo  by emailing to ewip[at the rate]unistring.com

Unifying Software & Hardware
Morphological image processing  - IP core

UTS-IMG-MORPH-V4



Contact us with your specifications for obtaining quote specific to your requirements.
Applications
Image processing
Video processing
Satellite applications
Digital electronic devices
Traffic monitoring systems
Bio medical applications
DSP applications
Key features
Architecture & Core description
Ordering information (P/N)
Area, Speed and Through put bench marks for Xilinix FPGAs
Tested on all Xilinx Spartan and vertex device FPGAs
High frequency of operation 175MHZ
Run time configurable gain terms
Area Optimized design (resource utilization benchmarks are given below)
Run time user loadable filter coefficients for pulse shaping
FIFO interface to Soft processor (microblaze) or Hard processor (ARM9 of Zynq)
Licensing terms
Block diagram
Other Required / Related IPs
   IP     Resource utiilztion
Wide band DDC  
UART  
Ethernet .
Contact UTS vlsi division for more details
   IP and configuration     Resource utiliztion Resource utiliztion
Resource
utiliztion

Speed
(max
freq)
Suitable usage
  Slices(Reg)
Used/available= %
DSP48
Used/available= %
Block RAM’S
   
Image-2D-filtering
Device:Spartan-3E
3273/9312-35%
4/20-20% 100MHZ
Image processing application
Image-2D-filtering Device:Vertex-6
2809/301440-1%
0/768-0% 0/832-0%
175MHZ
Image processing application
Neg_lin_con_dil_ero:
   IP and configuration     Resource utiliztion Resource utiliztion
Resource
utiliztion

Speed
(max
freq)
Suitable usage
  Slices(Reg)
Used/available= %
DSP48
Used/available= %
Block RAM’S
   
Image-2D-filtering
Device:Spartan-3E
3908/9312-41%

  6/20-30% 100MHZ
Image processing application
Image-2D-filtering Device:Vertex-6
3316/301440-1%
0/768-0%
0/832-0%
175MHZ
Image processing application
   IP and configuration     Resource utiliztion Resource utiliztion
Resource
utiliztion

Speed
(max
freq)
Suitable usage
  Slices(Reg)
Used/available= %
DSP48
Used/available= %
Block RAM’S
   
Image-2D-filtering
Device:Spartan-3E
1656/9312-17%

6/20-30% 100MHZ
Image processing application
Image-2D-filtering Device:Vertex-6
3315/301440-1%
0/768-0%
0/832-0%
175MHZ
Image processing application
Opening :
Closing :
Linear:
Negative:
Contrast:
Dilation:
Erosion:
Opening:
Closing: