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   IP and configuration     Resource utiliztion Resource utiliztion
Resource
utiliztion

Speed
(max
freq)
Suitable usage
  Slices(Reg)
Used/available= %
DSP48
Used/available= %
Block RAM’S
   
Image-2D-filtering
Device:Spartan-3E
1656/9312-17%
  17/20-85%
100MHZ
Control system application
Image-2D-filtering Device:Vertex-6
861/301440-0%
3/768-0%
0/832-0%
75MHZ
Control system application
For High Speed FPGA based Control Systems, PID controller is very common for implementing control systems. In several applications high speed digital parallel control will be required. A single PID controller can be multiplexed for multi channel realization. The UTS created IP core can meet such requirements in addition to legacy applications.
UTS offers IPs under flexible licensing models, to meet requirements of different category of users. The low cost reference designs are distinguished from IPs with less (or no) document (end user/project) execution for licensing.  Read more from IP main page.

UTS offers transparent and pre-committed pricing model for a minimum period of five years from the date of order  to migrate from per product based licensing to unlimited licensing or source code licensing models. With this the system developers have clear estimate of the cost in the volume production, right at the time of prototype development.


IP based on user specification

UTS also takes up development of complex algorithms based on the end performance specifications as per user requirements. In certain fields UTS also takes up this development on No cost - No commitment (NCNC) model. Based on the project category the UTS share on IP rights can be worked out for mutual benefit.

Refer to the links given for obtaining information of different IPs. Request for more information or demo  by emailing to ewip[at the rate]unistring.com

Unifying Software & Hardware
PID controller - Reference Design

UTS-CNTL-PID-V5 



Contact us with your specifications for obtaining quote specific to your requirements.
Applications
 
Industrial automation
Robotics
Temparature controlling
Automated navigation systems
Auto pilot
Key features
Architecture & Core description
Ordering information (P/N)
Area, Speed and Through put bench marks for Xilinix FPGAs
Tested on all Xilinx Spartan and vertex FPGA families.
High frequency of operation 100MHZ
Run time configurable gain terms
Area Optimized design (resource utilization benchmarks are given bellow)
Run time controllable thresholds
FIFO interface to Soft processor (microblaze) or Hard processor (ARM9 of Zynq)
Licensing terms
Block diagram
Other Required / Related IPs
   IP     Resource utiilztion
Wide band DDC  
UART  
Ethernet .
Contact UTS vlsi division for more details