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IP and configuration Resource utiilztion Maximum clock Speed
(max possible symbol rate)
M-PSK Modulator
Xilinx Virtex-6 FPGA
Slices -   22124
DSP48 - 56
BRAM -   24
  210 MHz
(15 Msps)
The PSK modulator and demodulator cores, provided by UTS are FPGA proven variable data rate IP cores, which can meet large class of wired and wireless communication needs. This IP core provides several run time controls, to make it suitable for software defined radio and cognitive radio applications.
UTS offers IPs under flexible licensing models, to meet requirements of different category of users. The low cost reference designs are distinguished from IPs with less (or no) document (end user/project) execution for licensing.  Read more from IP main page.

UTS offers transparent and pre-committed pricing model for a minimum period of five years from the date of order  to migrate from per product based licensing to unlimited licensing or source code licensing models. With this the system developers have clear estimate of the cost in the volume production, right at the time of prototype development.

IP based on user specification

UTS also takes up development of complex algorithms based on the end performance specifications as per user requirements. In certain fields UTS also takes up this development on No cost - No commitment (NCNC) model. Based on the project category the UTS share on IP rights can be worked out for mutual benefit.

Refer to the links given for obtaining information of different IPs. Request for more information or demo  by emailing to ewip[at the rate]unistring.com
Unifying Software & Hardware
PSK Modulator and Demodulator - IP core

UTS-MPSK-MOD-V2.1 (only modulator)
UTS-MPSK-DEMOD-V2.12 (only demodulator)

Contact us with your specifications for obtaining quote specific to your requirements.
High data rate FPGA proven PSK IP core
High band width point to point wireless links
Software Defined Radios
Cognitive Radios
UAV to Ground Communication
Satellite communication
Test equpiment
Military & Home land security
Key features
Architecture & Core description
Ordering information (P/N)
Area, Speed and Through put bench marks for Xilinix FPGAs
Tested on all Xilinx 5,6,7 device FPGAs
High frequency of operation - 250 MHz
Run time configurable symbol rates - 8 ksps to 12 Msps
     -- Date rate with BPSK : 8 Kbps to 12 Mbps
     -- Date rate with QPSK : 16 Kbps to 24 Mbps
     -- Date rate with OQPSK : 16 Kbps to 24 Mbps
     -- Date rate with 8-PSK : 24 Kbps to 36 Mbps
Area Optimized design( resource utilization benchmarks are given below)
Seletable pulse shaping filter (SRRC, RRC) and rolloff  factors
Runtime User loadable filter coefficients for pulse shaping
Run time controllable thresholds to work under different signal conditions (phase lock, symbol lock etc)
Automatic constellation rotation detection and symbol to bit decoding
FIFO interface to Soft processor (microbalze) or Hard processor (ARM9 of Zynq)
Ethernet software driver to interface to PC or Embedded unit over LAN
Licensing terms
Other Required / Related IPs


Wide band DDC When the input is from ADC (real signal), then DDC will be required to down convert to complex base band signal.
Time division mux and demux When multiple channel data need to be transmitted/received these multiplexers and demultiplexers are suitable to be used along with modulators and demodulators.
Channel encoders and decoders .In wireless communication at low SNRs, the channel encoders and decoders are appropriate to be used along with modulators and demodulators.
The PSK modulator and demodulator cores, provided by UTS are designed with speed and resource wise optimized techniques for FPGAs. The designs are tested for several corner cases, including tight placement constraints in small FPGAs and working at maximum clock rates. The block diagram of PSK modulator is given in below figure.
Fig. High level block diagram PSK modulator
The data rate controller blocks accepts the symbol rate word and generates "ready for bit" enable signal. The data sourcing FIFO can output one bit with this enable become '1'. The date rate controller block also generates enables for remaining logic for other modulator blocks based on symbol rate value. The bit to symbol mapping block generates I and Q symbols based on selected M-ary scheme (M=1,2,3 for BPSK, QPSK and 8-PSK) type. The pulse shaping block can perform optionally SRRC (square root raised cosine) or RRC (root raised cosine) with different roll off factors. Dynamically required filter coefficients can also be loaded.

The I and Q base band signals with/without pulse shaping are used to alter the instantaneous phase in phase accumulator block. The set carrier frequency is used to compute the unmodulated phase of carrier signal. The modulated phase is used to address the COS, SIN look up tables to produce complex modulated signal. The digital up converter (DUC) with fractional interpolator can produce output signal with required sampling rate. This feature enables driving any external Digital to Analog Converter (DAC) with required sampling rate.
Fig. High level block diagram PSK demodulator
The Digital Phase Locked Loop (DPLL) removes the phase offset in the input signal. The initial carrier frequency is the approximate carrier present in the input signal. The symbol timing recovery block computes one sample per symbol, by using timing error detector (TED) loop. Optionally the pulse shaping can be done for matched filtering. The detected I and Q can be can be used for plotting constellation. The symbol to bit mapping block can assign bits for each symbol based on the selected scheme. User can allocate any bit pattern for symbol, through run time configurable port.

This feature enables to use UTS - PSK demodulator with any frame synchronization modules such as E1/T1/E2/E3/T2/T3. The phase offset between transmitter and receiver can be compensated to ensure the frame synchronization is achieved. The demodulated symbol and bit are the final outputs of PSK demodulator.

The run time configurability of M-ary scheme (BPSK, QPSK and 8-PSK), symbol rate, carrier word makes the UTS PSK demodulator suitable for software defined radio and cognitive radio applications.
Verification of PSK on Xilinix FPGAs
Contact UTS for obtaining these details.
IP and configuration Resource utiilztion Maximum clock Speed
(max possible symbol rate)
M-PSK DeModulator
Xilinx Virtex-6 FPGA
Slices -   52229
DSP48 - 104
BRAM -   93
    240 MHz
   (15 Msps)
Note that these results are only indicative of approximate area utilization and speed. Depending on the required features, it is possible to further optimize to improve speed and reduce resouce utilization. Contact UTS for obtaining details specific to your target FPGA family and device.

Also note that major BRAM resources are used by Chipscope memory (for in chip debugging), which can be removed in the production version. At least 50% of BRAM resources will get reduced.