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The UTS Secure Arithmetic Coding (SAC) encoder and Decoder can provide security as well as source encoding for wired and wireless communications applications. In general for security requirements encryption and decryption are used and for encoding source encoders and Decoders are used which increases overall area occupancy in Radios. The UTS offered integrated solution is novel method for achieving security and arithmetic coding in a single core.
Unifying Software & Hardware
Secure Arithmetic Coding (SAC) - IP core
High data rate FPGA proven SAC - IP core
Key features
Ordering information (P/N)
Digital cameras
Portable music players
Other gadgets using JPEG2000 or H.264 standard
Software Defined Radios, Cognitive Radios
Miiltary & Home land security

Contact us with your specifications for obtaining quote specific to your requirements.
Tested on all Xilinx Spartan series 3, 3E, 601,605 devices and vertex device FPGAs
High frequency of operation - 50 MHz
Run time configurable data rates - User Programmable data clocks
Area Optimized design( resource utilization benchmarks are given below)
FIFO interface to Soft processor (microbalze) or Hard processor (ARM9 of Zynq)
Ethernet Software driver to interface to PC or Embedded to over LAN
Architecture & Core description
Block diagram: Secured encoder:
Secured decoder:
Contact UTS for obtaining these details.
Area, Speed and Through put bench marks for Xilinix FPGAs
   IP and configuration     Resource utiilztion     Speed(max
Suitable end usage
DSP48 Used/available-% Block RAM’S    

SAC-Device- Spartan3E

1593/ 4656  -  34%


Radio communications

SAC-Device:Sparta n605

552  /54576  -   1%

48  / 58 -  82% 

3 / 116 -   2% 

25 MHz

Radio communications

570 /301440 -  0%

56  / 768     7% 

3/  416     0%

25 MHz

Radio communications

   IP     Resource utiilztion
Wide band DDC  
Time division mux and demux  
Channel encoders and decoders .
Licensing terms
UTS offers IPs under flexible licensing models, to meet requirements of different category of users. The low cost reference designs are distinguished from IPs with less (or no) document (end user/project) execution for licensing.  Read more from IP main page.

UTS offers transparent and pre-committed pricing model for a minimum period of five years from the date of order  to migrate from per product based licensing to unlimited licensing or source code licensing models. With this the system developers have clear estimate of the cost in the volume production, right at the time of prototype development.

IP based on user specification

UTS also takes up development of complex algorithms based on the end performance specifications as per user requirements. In certain fields UTS also takes up this development on No cost - No commitment (NCNC) model. Based on the project category the UTS share on IP rights can be worked out for mutual benefit.

Refer to the links given for obtaining information of different IPs. Request for more information or demo  by emailing to ewip[at the rate]unistring.com
Other Required / Related IPs