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The software defined radio (SDR) transceiver core, provided by UTS are FPGA proven IP core, which can be configured for different  modulation types and data rates at run time. This IP core provides several run time controls, to make it suitable for military applications.
UTS offers IPs under flexible licensing models, to meet requirements of different category of users. The low cost reference designs are distinguished from IPs with less (or no) document (end user/project) execution for licensing.  Read more from IP main page.

UTS offers transparent and pre-committed pricing model for a minimum period of five years from the date of order  to migrate from per product based licensing to unlimited licensing or source code licensing models. With this the system developers have clear estimate of the cost in the volume production, right at the time of prototype development.

IP based on user specification

UTS also takes up development of complex algorithms based on the end performance specifications as per user requirements. In certain fields UTS also takes up this development on No cost - No commitment (NCNC) model. Based on the project category the UTS share on IP rights can be worked out for mutual benefit.

Refer to the links given for obtaining information of different IPs. Request for more information or demo  by emailing to
ewip@unistring.com
Unifying Software & Hardware
SDR Transciever - IP core

UTS-SDR-V2 (MODEM),
UTS-SDR-MOD-V2.1 (only modulator)
UTS-SDR-DEMOD-V2.7 (only demodulator)

Contact us with your specifications for obtaining quote specific to your requirements.
Applications
High data rate FPGA proven Software Defined Radio Transciever IP core
High band width point to point wireless links
Congnitive Jamming
Cognitive Radios
ESM / ELINT
UAV to Ground Communication
Satellite communication
Test equpiment
Miiltary & Home land security
Key features
Architecture & Core description
Ordering information (P/N)
Area, Speed and Through put bench marks for Xilinix FPGAs
Run time selection of modulation type M-PSK, M-QAM, M-NCFSK, M-CFSK
Run time configurable symbol rates - 8 ksps to 12 Msps
     -- Date rate with QAM-4 :  16 Kbps to 24 Mbps
     -- Date rate with QAM-8 :  24 Kbps to 36 Mbps
     -- Date rate with QAM16 : 32 Kbps to 48 Mbps
     -- Date rate with QAM32 : 40 Kbps to 60 Mbps
     -- Date rate with QAM64 : 48 Kbps to 72 Mbps
     -- Date rate with PSK-2 :  8 Kbps to 12 Mbps
     -- Date rate with PSK-4 :  16 Kbps to 24 Mbps
     -- Date rate with PSK-8 :  24 Kbps to 36 Mbps
     -- Date rate with FSK-2 :  8 Kbps to 12 Mbps
     -- Date rate with FSK-4 :  16 Kbps to 24 Mbps
Run time selectin of mode: Simplex, Half Duplex and Full duplex
Tested on all Xilinx 5,6,7 device FPGAs
High frequency of operation - 250 MHz
Run time configurable carrier frequency.
Area Optimized design
Selectable pulse shaping filter (SRRC, RRC,Gaussian) and rolloff  factors
Runtime User loadable filter coefficients for pulse shaping
Run time controllable thresholds to work under different signal conditions (phase lock, symbol lock etc)
Automatic constellation rotation detection and symbol to bit decoding
FIFO interface to Soft processor (Microblaze) or Hard processor (ARM9 of Zynq)
Ethernet software driver to interface to PC or Embedded unit over LAN
Licensing terms
Other Required / Related IPs

   IP

    Purpose
Wide band DDC When the input is from ADC (real signal), then DDC will be required to down convert to complex base band signal.
Time division mux and demux When multiple channel data need to be transmitted/received these multiplexers and demultiplexers are suitable to be used along with modulators and demodulators.
Channel encoders and decoders In wireless communication at low SNRs, the channel encoders and decoders are appropriate to be used along with modulators and demodulators.
The SDR transceiver IP core posses the capabilities UTS-PSK, QAM, NCFSK and CFSK MODEM IP cores. Read the respective IP pages for architecture details. Novel digital signal processing techniques are used to combine these modulator and demodulator schemes in area optimized core. Depending on the user requirements this core can be modified to include or remove modulation types. Contact us for further customization of SDR IP cores.
Verification of QAM on Xilinix FPGAs
Contact us for details
Contact us for details