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In FPGA based designs, the user RTL logic requires run time personalization based on external inputs. Designers need to spend considerable amount of time to establish such logic in their application. UTS provided UART based Register Configure/Read IP Core provides simple byte encoded UART towards PC/Embedded application and can maintain 32 bit wide Register Read/Write interface in FPGA (for RTL logic).
UTS offers IPs under flexible licensing models, to meet requirements of different category of users. The low cost reference designs are distinguished from IPs with less (or no) document (end user/project) execution for licensing.  Read more from IP main page.

UTS offers transparent and pre-committed pricing model for a minimum period of five years from the date of order  to migrate from per product based licensing to unlimited licensing or source code licensing models. With this the system developers have clear estimate of the cost in the volume production, right at the time of prototype development.

IP based on user specification

UTS also takes up development of complex algorithms based on the end performance specifications as per user requirements. In certain fields UTS also takes up this development on No cost - No commitment (NCNC) model. Based on the project category the UTS share on IP rights can be worked out for mutual benefit.

Refer to the links given for obtaining information of different IPs. Request for more information or demo  by emailing to ewip[at the rate]unistring.com
Unifying Software & Hardware
UART BASED REGISTER CONFIGURE/READ-IP Core




UTS-UART -REG-V5 (REGISTER READ/WRITE)
Contact us with your specifications for obtaining quote specific to your requirements
Applications
Flexible UART based register read/write solution for FPGA design



Key features
Architecture & Core description
Ordering information (P/N)
Area, Speed and Through put bench marks for Xilinix FPGAs
Tested on all Xilinx 3, 4,5,6,7 device FPGAs
Maximum Register addresses – 256
Register read/write data width - 32
High frequency of operation - 50MHz
Area optimized design 
FIFO interface to Soft processor (microblaze) or Hard processor (ARM9 of Zynq)
Ethernet software driver to interface to PC or Embedded unit over LAN(optional)
Licensing terms
Other Required / Related IPs
Figure: Block Diagram of UART Register Configuration
The above figure shows block diagram of UART Register Configuration. Data read from PC through UART and it is stored in a Register. There are two registers connected to a BRAM, named Read only and Write only. These Registers are also connected with the RTL Logic to access data.
Verification of FSK on Xilinix FPGAs
Software Defined Radio
Test equipment
FPGA based industrial automation
Data acquisition systems

Contact UTS for obtaining these details.

Contact UTS for obtaining these details.

Contact UTS for obtaining these details.