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Realizing FPGA based systems demand for variety of interface requirements for external connectivity. Having design on FPGA systems it is also desired to maintain real time interface with the external peripherals. UTS provided FPGA based interfacing solutions ensure real time configurability to meet variety of applications. In legacy designs, external microcontrollers are used to achieve serial or parallel interface to FPGA’s. UTS provided low area interface solutions avoid the necessity of external microcontroller IC. The interface IP’s occupying less resources on FPGA are able to give real time interface to the external peripheral without demanding for additional microcontroller IC’s. UTS I2C IP Core is a drag and drop IP with highly area optimized design.
UTS offers IPs under flexible licensing models, to meet requirements of different category of users. The low cost reference designs are distinguished from IPs with less (or no) document (end user/project) execution for licensing.  Read more from IP main page.

UTS offers transparent and pre-committed pricing model for a minimum period of five years from the date of order  to migrate from per product based licensing to unlimited licensing or source code licensing models. With this the system developers have clear estimate of the cost in the volume production, right at the time of prototype development.

IP based on user specification

UTS also takes up development of complex algorithms based on the end performance specifications as per user requirements. In certain fields UTS also takes up this development on No cost - No commitment (NCNC) model. Based on the project category the UTS share on IP rights can be worked out for mutual benefit.

Refer to the links given for obtaining information of different IPs. Request for more information or demo  by emailing to ewip[at the rate]unistring.com
Unifying Software & Hardware
Inter Integrated Circuit - IP Core


UTS-I2C -V5
Contact us with your specifications for obtaining quote specific to your requirements
Applications
High speed communication FPGA IP core

Key features
Architecture & Core description
Ordering information (P/N)
Area, Speed and Through put bench marks for Xilinix FPGAs
Tested on all Xilinx 3, 4,5,6,7 device FPGAs
High frequency of operation - 50MHz
FIFO interface to Soft processor (microblaze) or hard processor (ARM9 of Zynq)
Ethernet software driver to interface to PC or Embedded unit over LAN (optional)
Licensing terms
Other Required / Related IPs
Figure: Block diagram of I2C protocol
I2C has two wires SDA and SCL. SDA is the Serial Data line and SCL is the Serial Clock Line. The I2C bus is a multi-master bus, more than one IC capable of initiating a data transfer can be connected to it. In the I2C protocol, the IC that initiates a data transfer on the bus is considered the Bus Master. Consequently, at that time, all the other ICs are regarded to be Bus Slaves.
Verification of FSK on Xilinix FPGAs
Software Defined Radio
Memory applications
Communication protocols
FPGA based industrial automation
Data acquisition systems

Contact UTS for obtaining these details.

Contact UTS for obtaining these details.

Contact UTS for obtaining these details.