Web Unistring

Copyright 2006 - Unistring Tech Solutions Pvt. Ltd., INDIA

More
More
More
More
Realizing FPGA based systems demand for variety of interface requirements for external connectivity. Having design on FPGA systems it is also desired to maintain real time interface with the external peripherals. UTS provided FPGA based interfacing solutions ensure real time configurability to meet variety of applications. In legacy designs, external microcontrollers are used to achieve serial or parallel interface to FPGA’s. UTS provided low area interface solutions avoid the necessity of external microcontroller IC. The interface IP’s occupying less resources on FPGA are able to give real time interface to the external peripheral without demanding for additional microcontroller IC’s.
UTS UART IP core is dynamically configurable (Baud rate, data bits, and stop bits) with highly area optimized design.  This IP core also has an option of adding noise removing filters before decoding to ensure its usability in noisy/long distance links.
UTS offers IPs under flexible licensing models, to meet requirements of different category of users. The low cost reference designs are distinguished from IPs with less (or no) document (end user/project) execution for licensing.  Read more from IP main page.

UTS offers transparent and pre-committed pricing model for a minimum period of five years from the date of order  to migrate from per product based licensing to unlimited licensing or source code licensing models. With this the system developers have clear estimate of the cost in the volume production, right at the time of prototype development.

IP based on user specification

UTS also takes up development of complex algorithms based on the end performance specifications as per user requirements. In certain fields UTS also takes up this development on No cost - No commitment (NCNC) model. Based on the project category the UTS share on IP rights can be worked out for mutual benefit.

Refer to the links given for obtaining information of different IPs. Request for more information or demo  by emailing to ewip[at the rate]unistring.com
Unifying Software & Hardware
Universal Asynchronous Receiver Transmitter-IP Core

UTS-UART-TRANS-V5 (Receiver and transmitter)

Contact us with your specifications for obtaining quote specific to your requirements
Applications
High speed dynamically baud rate configurable FPGA IP core
Key features
Architecture & Core description
Ordering information (P/N)
Area, Speed and Through put bench marks for Xilinix FPGAs
Tested on all Xilinx 3, 4,5,6,7 device FPGAs
High frequency of operation - 50MHz
Run time configurable data rates
–Baud rate 9600 or 115200
–Data bits 7 or 8
–Stop bit 1 or 2
Area optimized design (resource utilization benchmarks are given below)
Noise removing decimation filters (optional)
Ethernet software driver to interface to PC or Embedded unit over LAN (optional)
FIFO interface to Soft processor (microblaze) or hard processor (ARM9 of Zynq)
Licensing terms
Other Required / Related IPs

                   IP

                                                      Purpose
        
        Ethernet , 1553
While realizing end to end data acquisition, interfacing solutions it is desired to have industry standard Ethernet or 1553 to the external peripherals.
Browse respective IP pages for more details.
Figure: Block Diagram of UART
The UART performs serial-to-parallel conversion on data received from a peripheral device or a modem on data received from the CPU. Transmission operation is simpler since it is under the control of the transmitting system. As soon as data is deposited in the shift register after completion of the previous character, the UART hardware generates a start bit, shifts the required number of data bits out to the line, generates and appends the parity bit (if used), and appends the stop bits. The enable generator is used to individually enable or disable each type of request that can be generated by the UART. Each request that is enabled in enable register is forwarded to the CPU. The Receiver tests the state of the incoming signal on each clock pulse, looking for the beginning of the start bit. If the apparent start bit lasts at least one-half of the bit time, it is valid and signals the start of a new character. If not, it is considered a spurious pulse and is ignored..
Verification of FSK on Xilinix FPGAs
Software Defined Radio
Test equipment
FPGA based industrial automation
The above figure shows chipscope results of UART with baud rate 19200, data bits 8 and stop bit 1.
Note that these results are only indicative of approximate area utilization and speed. Depending on the required features, it is possible to further optimize to improve speed and reduce resource utilization. Contact UTS for obtaining details specific to your target FPGA family and device.

Also note that major BRAM resources are used by Chipscope memory (for in chip debugging), which can be removed in the production version. At least 50% of BRAM resources will get reduced.